Future Directions

We are committed to continually improving our technology, and this commitment is reflected by an ongoing program of Research and Development in new processes, new capabilities, and new approaches to computer design that will facilitate novel applications. The emphasis is always on increased performance, increased efficiency, and on versatile and simple programming. Some of this work is evolutionary, meaning that it may lead to generally upward compatible improvements in our existing architectures. Some is frankly revolutionary, such as introducing entirely new computers. When we can share the status of these efforts without compromising our position, we shall do so and will appreciate feedback.

This section documents new design perspectives that are still in the process of refinement and which may, or may not, be expressed in future products. Anyone whose entrepreneurial goals call for greater commitment or more rapid development is invited to collaborate with us through a suitable vehicle such as funding, investment, or possible joint ventures; please contact Business Development to explore options.

18-bit Architecture for Ubiquitous Computing

Our 18-bit chips are important for conservation of cost and energy in embedded systems. They directly address the requirements of the huge, emerging market that has been referred to by terms such as "Machine-to-Machine" or "the Internet of Things." The key characteristic of this market is the huge numbers of units envisioned; not mere hundreds of millions, but tens to hundreds of billions. When planning to manufacture ten to the tenth or eleventh power of items, cost rules; when planning to deploy them, energy efficiency and maintenance cost rule. Conventional computers, running legacy operating systems and legacy software, were never designed to address these three crucial considerations. On the other hand, our 18-bit computers and chips have been designed specifically to address them. We expect that anyone who makes good use of our technology to develop devices for these huge, emerging markets should experience the pleasure of a commanding competitive position in manufacturing cost, energy efficiency, and maintenance costs. We are therefore actively collaborating with developers of such devices to help them realize these benefits. If your company has such plans, you may try to field yet another unix platform, but we predict you will lose to our customers in the marketplace. Why not join them instead?

F18X Chip Technology

We are working on evolutionary improvements in the design and implementation of our F18A based chips. This process started with F18B technology and prototype chips based upon it: ESD protection is improved by new pad design, address space is simplified to shorten code, and I/O improvements include executing a pin for wakeup and automating the setting of wakeup direction, simplifying I/O code and reducing its power consumption. Further improvements are being developed for the next prototyping run, including significant advancements in energy conservation and reduction in minimal operating supply voltage, enlarging the operational VT (Voltage-Temperature) envelope. The F18X technology is generally upward compatible with the F18A; although some code changes will be required, these will generally earn the effort by reducing program memory requirements and minimizing energy consumption.

F18B Computer

F18B Computer

F18B I/O

F18B I/O

F18B Briefs

GA4-1.2 Chip

GA4-1.2 Chip

GA4 Chip Information

Downloadable arrayForth Software Support
Quick Reference Poster

Status

A limited number of these prototype chips exist, in 8-pin and 12-pin packages. There is no guarantee they will ever be produced. Contact us if you have a bona fide research interest in using a small number of them.

32-bit Architecture for Efficient Crunching

Some applications, such as advanced vision and decision making systems found in UAVs (Unmanned Aerial Vehicles), "Big Data" such as massive search engines, and modern cryptography, make continually increasing demands for computing performance but are unable to afford even proportionally increasing supplies of power. For various reasons, semiconductor process technology is having increasing difficulty in providing the continual improvements in useful work accomplished per joule expended necessary to support the increasing demands of such applications. We believe that the wisest way to ameliorate this problem is to abandon the legacy software that has been driving conventional computer architectures and address these demanding problems in a fresh, far simpler way. Accordingly, we began designing a completely new computer with 32-bit data paths, advanced arithmetic capabilities, and an entirely new instruction set; using this computer, we would be able to build chips and program them to set a new standard in computational application performance per unit energy expended. Further effort on this project may be triggered by customer interest sufficient to warrant the substantial investment.

Improved F18 and GA144 chip

We have been developing significant hardware improvements for the F18 computer (principally concerned with further reducing energy consumption) and for the G144A12 chip (such as on-chip bulk memory, ability to re-assign the 36 I/O pins currently reserved for parallel ports to access external memory) in such a manner as to remain upward compatible in both pin-out and software. As funding is available we expect to take this design work to silicon.

Software Development Tools

Collectively named by the arrayForth brand, our initial software development system was derived from the CAD system used to design the chips themselves. It was based on colorForth running on the x86 instruction set and was fully supported on Win32 platforms such as Microsoft Windows, as well as compatible environments on Apple Mac and on Unix platforms. These tools enabled interactive software development and testing on our chips using serial communications at rates up to 1 megabit per second.

The next generation of software development tools runs on both the x86/Win32 platform and also directly on our chips using a Virtual Machine running a high level polyFORTH system. Named arrayForth 3, this development environment has been released and is fully supported, supplanting the older version of arrayForth that was based on colorForth. Future plans for this system include:

Because our chips are fully capable of standalone software development, this allows the Evaluation Board to replace the PC in that role with the benefits of far faster and more intimate communications with the node(s) and/or chips(s) under test and of a far more flexible development platform. This could lead to a development system packaged as a very small module with Ethernet or USB communications and with a suitable connector for communication with the prototype system under development; in addition to communication for programming and debugging, this connector could provide high speed, high impedance I/O pins for use in stimulating the target circuit with analog or digital signals, as well as probing the circuit non-invasively.

etherForth

Chuck Moore, indefatigable as always in his quest to create a programming environment more pleasing to him than its predecessor, embarked several years ago on an adventure with our chip in which no holds were barred, no cattle were sacred, and no convention was unquestioned. Chuck named this project etherForth, and in 2020 graciously authorized Daniel Kalny to revive, document and publish it. You will find linkage to Daniel's efforts on our Customer Support Central page.