GA144 144-computer Chip

The chip measures 4.7 x 4.5 mm in a 180 nm process. That size was chosen because it is the largest chip we can presently package in the 10x10 mm QFN-88. 104 pads border the chip (16 ground pads connect to the exposed die attach paddle; 16 power pads and 72 signal pads connect to the 88 pins on the edges of the package) and 8 rows of 18 computers fit inside.

Low power results from our computer (one node of an array) being asynchronous (unclocked). Low energy results when each of the 144 computers is executing instructions only when it actually has something to do. Spec sheets will be forthcoming. Meanwhile this list of features should prove impressive. Bill Muench composed a handy poster with much info.

GA144 has 88 pins. Pins are numbered counter-clockwise from upper left.

• 18 pins for RAM data: 1 2 3 8 9 10 11 12 13 16 21 22 23 24 25 30 31 32
• 18 pins for RAM address: 37 38 39 42 43 44 45 46 53 54 55 56 57 58 65 66 67 68
• 16 pins for Vdd (1.8 V): 4 5 17 19 28 29 40 41 47 49 62 64 74 75 82 83
  Vss is the ground/heat-sink on the bottom of the package.
• Reset: 88
• 25 digital I/O: 6 7 14 15 18 20 26 27 33 34 35 36 51 52 59 60 71 78 79 80 81 84 85 86 87
• 5 D/A outputs: 50 63 70 72 77
• 5 A/D inputs: 48 61 69 73 76

22 of the edge computers have one or more I/O pins, with specialized ROM; six of these are capable of being used to boot the chip after reset. The 96 interior computers, and the 26 edge computers that don't have I/O pins, all have the same ROM with five exceptions noted below. Any of the 144 computers may be used as compute engines, as wires to pass messages, or simply left fallow with minimal power leakage; the 22 edge computers with I/O pins are assigned nominal functions based on their ROM and I/O pads. These nominal functions are as follow, by three digit node number:

• 001: digital 26 27; SerDes (BOOT)
• 007: RAM data (Nodes 007,8,9 have ROM support for external SDRAM)
• 008: RAM control 33 34 35 36
• 009: RAM address
• 100: digital 20
• 117: analog 48 50
• 200: digital 18; 1wire (BOOT)
• 217: digital 51 (analog trigger for 117)
• 300: digital 14 15; Sync (BOOT)
• 317: digital 52
• 417: digital 59
• 500: digital 7
• 517: digital 60 (analog trigger for 617)
• 600: digital 6
• 617: analog 61 63
• 701: digital 86 87; SerDes (BOOT)
• 705: digital 80 81 84 85; SPI (BOOT)
• 708: digital 78 79; Async RS232 compatible (BOOT)
• 709: analog 76 77
• 713: analog 73 72
• 715: digital 71 (analog trigger for 709,13,17)
• 717: analog 69 70

Features

• 2.4 pF I/O pad capacitance (inclusive of ESD)
• 1.8V Vdd +- 10%
• 3 mA per node that's running; 100 nA if sleeping (leakage)
• Powers-up in reset
  • Draws no power
  • High on pin 88 takes chip out of reset
• Implements the colorForth instruction set
• Built in ROM support for SDRAM (nodes 007,8,9,107,8); for high level language interpretation (nodes 105,6); and for DMA device (node 207).

• Digital communication
  • Nodes 007,8,9 as 36 bit parallel 2.77 GBPS
  • Node 705 (4 wire as 3 bit parallel) to 250 MBPS
  • Asynchronous (RS232 compatible timing) to 20 MBPS, possibly 33. Max of 8 2-wire interfaces => 160 MBPS.
  • Synchronous (2 wire clock and data) to 39 MBPS. Max of 8 2-wire interfaces => 312 MBPS.
  • 1-wire PWM suitable for DC or AC (series capacitor) coupling to 23 MBPS. Max of 13 1-wire interfaces => 299 MBPS.
  • Serializer/Deserializer 400 MBPS. Max of 2 => 800 MBPS.

• D/A out
  • 9-bits of scaled current source into a nominal 75 ohm load
  • Range from 0 to 1.5 V into 75 ohms, generally proportional to load.
  • Moderate non-linearity correctable with software or op-amp
  • Drivers designed to minimize glitches
  • About 30mA max current (TBD)

• A/D in
  • VCO with 18-bit counter
  • Averages value over sample interval (low-pass filter)
  • 6-bit resolution at 10 MHz, 17-bit at 10 KHz
  • Range from .5 to 1.3 V
  • Moderate non-linearity correctable with software
  • Triggerable from neighboring node
  • Internal calibration at Vdd and Vss
  • Reset to Vdd input with VCO turned off allows no-connect of pin

• Digital I/O (all but 18-bit buses)
  • 4 modes for each pad:
    • Output high (1.8 V)
    • Output low
    • Input (very high impedance, 10-100 Megohms, TBD)
    • Input with weak (50KOhm) pull-down (default at reset) capable of sinking 41 uA in saturation (shorted).
  • 20 ohm output drivers; max sourced 48 mA, sunk 41 mA in saturation (shorted).
  • Pad connected to bit 17 of IO register convenient for input (can be tested as sign bit)
  • Bit 17 high or low can wake up node
  • Pull-down allows no-connect of pin

• Wake-up
  • A node can sleep (using no power) by reading the wake-up port. It can wake up when input goes high or low (level detect)
  • Such wake-up synchronizes the node to the input edge, with a phase jitter of picoseconds. The input node can synchronize other nodes via the internal communication ports