Realities Dictated by Technology

A given technology yields a given set of characteristics in terms of natural performance and energy efficiency. Here are examples from processes we are familiar with.

180nm CMOS

This is a mature process that is available from multiple foundries and probably will be for many years. It is the process currently being used to fabricate our GA4, GA32, and GA144 chips. For logic, we design for a 1.8v power supply.

A minimal design built using this technology will have certain natural characteristics, as we have learned:

Behavior of minimal devices

A minimal N transistor (see cursor) is capable of perhaps 450 microamperes or 800 microwatts in saturation. Thus in saturation the device looks like a 4000 ohm resistance. The minimal P transistor, to its left but about twice as wide in order that the inverter of which both are members be balanced, is capable of about 350 uA (microamperes). At the instant shown, the N device is conducting 210 uA.

Capacitance of minimal loads

The capacitive load represented by a very short metal trace to, and including, the gate of a minimal inverter just like the one shown, is on the order of 8 femtofarads. A simple time constant (T=RC) for this minimal N device driving that capacitive load is on the order of 32,000 femtoseconds or 32 picoseconds. In simulation and in measured reality such a network on our chips moves from rail to rail in about 100 picoseconds, or about 3 of these time constants, which is reasonably consistent; here is a simulation of the output of this very inverter, cold, shown falling between the cursors in the next to bottom yellow trace below:

Energy Required to Switch an Inverter

In the above simulation, the final traces below the yellow that probes the inverter's output voltage are red and green. These depict the power being dissipated in the (green) N and (red) P devices composing the inverter. The scale of this trace is such that the peak value of the green trace, power being dissipated in the device that is pulling the charge on the 8 femtofarad output capacitance down to ground, peaks at a little over 250 microwatts. This is a huge amount of power at our scale, and yet this is practically the most trivial, low energy device in a computer.

The number 14,245,674, on the bottom line in yellow, is the integral of this power (in nanowatts) over the time (in picoseconds) during which the inverter changed state. Thus, the integral is in units of zeptoJoules - one zJ being ten to the minus 21st Joules. So, changing the state of this inverter cost us 14.25 femtoJoules (fJ), meaning then that if we are given one Joule of energy (one watt second) to work with, we will have been able to cause 70 trillion (70 times ten to the 12th) inverters to change state before we have used up the entire supply of energy we were given.

This simulated number passes sanity checks with our physical measurements of power on real chips, and so what 180 nm CMOS tells us is that the amount of work we will be able to do for our Joule of energy can be perhaps seventy billion instructions worth if we hold the line on simplicity; or we can cut that way down by relaxing our discipline, as so many others have done. It is generally axiomatic that adding complexity adds gates; complexity has costs in many dimensions, and interestingly enough one of these can easily be a large increase in energy consumption.