Featured G144A12 Application Notes

We continually produce documents containing information of value to anyone using our chips. In the interest of placing useful information in your hands as soon as we can, some of this material is posted in informal form or as preliminary drafts of formal documents. We are also posting raw data from chip characterization and testing, so that the foundations of the specifications in our data sheets will be clear. Please contact our Hotline for any questions or comments regarding this content; if you wish to be informed of updates, please subscribe to the RSS feed on our blog.

This page shows only selected documents. For the full set of available App Notes please see the Download Index. In addition, the arrayForth Institute offers expanded coverage of app notes.

Hardware Design

These items pertain to hardware application of our chips, including examples of PCB (Printed Circuit Board) layout.

Complete Systems

EVB001 Evaluation Board (Last updated 9/26/2011) With two GA144 chips and great flexibility, this board is slated to become the primary hardware and software development platform for GreenArrays chips. It will be the reference or target system used in most of the documents below.

PCB Examples

SRAM Development Board (Last updated 7/11/2011) A simple PCB that was used for initial development of the eForth and polyFORTH virtual machines based on external SRAM.

Lower Cost Experimentation

Breadboarding on a Budget is a page devoted to making our chips accessible to experimenters whose designs are at the interactive breadboarding stage or for any other reason not yet appropriate for PCB layout.


The topics in this section include design, construction, and testing of software for our chips.

arrayForth Tools

Interactive Development Environment (IDE) (Last updated 4/05/2010) Internal documentation of the primary tool for incrementally, interactively testing and debugging F18 code for one or more computers in vivo on real chips.


Port Execution (Last updated 10/21/2014) A simplified demonstration of controlling a neighbor node by feeding it instructions over a COM port.

Design Exercises

These are application studies illustrating approaches to problem solving using our chips; some of these techniques might be useful in your designs. Complete source code is included.


AN001: MD5 Hash (Last updated 10/23/2014)

Hardware/software Modules

AP002: Simple oscillators (Last updated 9/10/2010) A hardware/software development exercise presented in the form of a tutorial diary to demonstrate process.

AN009: Attaching a PS/2 Keyboard (Last updated 9/12/2012) Stefan Mauerhofer builds a simple interface to the 5V PS/2 keyboard using a level shifter and F18 software.

AN016: Incremental PID Controller (Last updated 11/11/2014) Daniel Kalný controls the speed of a brushed DC motor equipped with an optical encoder using a software PID controller in a closed loop system.

Interfacing with Sensors

AN008: Exploring a 3-axis Accelerometer (Last updated 5/10/2012) Peter Milford demonstrates a very high-level method for interactively checking out a multi-node SPI interface and for verifying the protocol used with an interesting sensor.

AN012: Controlling the TI® SensorTag (Last updated 6/06/2013) The Texas Instruments SensorTag provides an excellent set of devices on a small, inexpensive platform. This exercise demonstrates various choreographic and programming techniques, primarily toward minimizing energy consumed per unit useful work. In this application we demonstrate the GA144's ability to maintain continuous situational awareness while operating from a coincell at an average power of 363 microwatts. Included is a practical use of the single-pin, software-defined 32.768 kHz crystal oscillator.

Module Library

These application modules are incorporated in released software products and are supported as such. You are of course invited to learn from them, adapt them to your needs, or simply employ them in your designs. Complete source code is included.

Software-Defined I/O

AP003: SRAM Control Cluster, Mark 1 (Last updated 8/10/2011) Four nodes provide a versatile but simple interface to external SRAM that may be shared by several masters, such as our virtual machines.

AN007: Software-Defined NIC 10baseT full duplex, Mark 1 (Last updated 11/12/2014) A software-defined full duplex 10baseT Network Interface Controller is implemented as a team of nodes controlling transmit and receive signal pins directly. The signals are conditioned by minimal electrical interface circuitry. External transmit timing is used. The team is designed to function as a memory-mapped device but may be stripped down for direct use by other node teams. This NIC is supported by the polyFORTH® TCP/IP package on the host chip of the EVB001 Evaluation Board.

AN010: The Snorkel Mark 1 (Last updated 6/04/2013) A programmable DMA channel implemented as a single-node external memory master.

AN011: Ganglia Mark 1 (Last updated 6/08/2013) This paper describes a means for exchanging message transactions between nodes that do not share a common COM port using message frames whose headers hold source routing information that is updated incrementally as the frame moves between contiguous nodes that have been programmed to serve as part of a surface, or fabric, for this purpose.

Major Applications

These items describe complete applications for our chips, which may be adapted. Complete source code is included.

Virtual Machines

DB005: polyFORTH® Reference Manual (Last updated 8/25/2012) Emulate a simple Virtual Machine using a handful of nodes, then program that virtual machine with a high level operating system. Use it to develop and run applications that demand greater resources at reasonable performance.

Automated Testing System

Raw Data

The numbers in our data sheets summarize data obtained by empirical testing. These items provide access to the raw data for the benefit of anyone wishing a deeper understanding of the summary numbers.


Raw Characterization Data (Last updated 5/07/2011) Primary data taken on 5 chips from each of 10 wafers representing a corner split lot for process variation, with measurements of sensitivity to variation in VDD and ambient temperature.

Valid XHTML 1.0 Strict